Parallel binary adder-subtracter circuits



sept. 27, 1960 J. L.. MADDox 2,954,168

VPARALLEL. BINARY ADDER-SUBTRACTER CIRCUITS Filed NV. 21, 1955 4 SheetsSheet l /N Pu 7' REQ-l5 TER J4 5ms.

HCCL/ML/LHTR N/LSTER RHA/K IN VEN TOR. f5/755 L. MHDDX MoJ-254i.,

Sept. 27, 1960 l y 1 L', MADDQX 2,954,168 PARALLEL BNARY ADDER-SUBTRACTER CIRCUITS Filed NOV. 21, 1955 4 Sheets-Sheep;y 2

' -Vcc CHER/V Sept? 27, 1950 J. l.. MADDox v 2,954,168

PARALLEL BINARYA ADDER-SUBTRACTER CIRCUITS Filed Nov. 21; 1955 4 sheets-sheet s 74a 744 74e 74d IN VEN TOR. 7H/7.55 l.. MHDDX Sept. 27,1960 1 MADDOX K 2,954,168

' PARALLEL BINARY ADDER-SUBTRACTER CIRCUITS Filed Nov. 21, 1955 4 Sheets-Sheet 4 352 Tlf HCC PARALLEL nstARY Annan-SUBTRACTER Cmcurrs Filed Nov. 21, 195s, ser. No. 548,030 16 claims. (ci. zas-17s) The present invention relates to computer circuits and more particularly to adder-subtracter circuits for use in digital computers. Y

Computer circuits may employ an adder circuit, a subtracter circuit or a combined adder-subtracter circuit as required by the intended function of the computer. In a typical binary computer employing parallel transfer of data, the adder subtracter circuit may receive the addend or subtrahend from the input register and the augend or minuend from the master rank of a two rank accumulator register. In the conventional formof addersubtracter circuits, n substantially identical adder-subtracter stages are provided, where n is the digital capacity of the input register and the accumulator master rank. Each stage is arranged to receive one digit from a corresponding bi-stable circuit in the input register, a second digit from a corresponding bi-stable circuit in the accumulator master rank and a carry or borrow digit from the next lower order adder-subtracter stage. Y Each Yaddersubtracter stage supplies a signal to still another register, this signal being representative of the sum or difference of the digits supplied by the input register, the accumulator master rank and the carry or borrow digit from the next lower order adder-subtracter stage. It also provides a carry or borrow signal which is supplied to the next higher order adder-subtracter stage. The parallel transfer of digits lfrom the input register and the accumuice, i

Y 2 indicate a sum of zero and a carry of onel The time required to accomplish this resetting will depend on the circuit constants of the adder-subtracter stage but is typically of the order of a tenth of a microsecond. The carry from the next to the'lowest order stage will be propagated to the next higherorder stage where another tenth of a microsecond will be yexpended in resetting this stage. In the example chosen above, this resetting operation will proceed in a serial fashion through the nineteen lower order stages, taking of the order of a tenth of a microsecond per stage to accomplish the resetting operation. Therefore the entire time required to accomplish an addition step if a ripple is present is of the order of two microseconds. This should be contrasted to an add time without ripple of one .or two tenths of a microsecond, In general, a computer having a capacity of n bits or digits and requiring s seconds to accomplish the resetting operation will ,have a maximum carry or borrow ripple time of Vns seconds. In most instances it is not practical to provide gating circuits for determining the completionof the carry ripple for every possible combination of addend and augend or subtrahend and minuend. Therefore it is the usualpractice to allow a time equal tothe maximum possible ripple'time for each addition or subtraction step.

ri'he disadvantages of the serially propagated carry ripple have been recognized in the past and circuits for providing simultaneous carry propagation have been proposed. In these proposed arrangements, gate circuits connect each adder-subtracter stage to all preceding stages. All carries are generated simultaneously in this arrangement so that ripple time is completely eliminated.

l The disadvantage of this proposed system lies in the fact lator to a plurality of adder-subtracter'stages is employed in the interest of minimizing the time required to perform an addition or subtraction step.

One factor which limits the maximum rate of operation of multi-digit parallel adder circuits, subtracter circuits or combined adder-subtracter circuits is the carry or borrow ripple which is propagated from the lowest order digit toward the higher order digits. For example, suppose that in a twenty digit computer a carry is indicated in the lowest order adder-subtracter stage. The occurrence of a carry in the lowest order stage may cause a carry to be present in the output of the next higher order stage where no carry existed before. If this is true, the sum and carry signal of the third and perhaps all higher order stages maychange in response to the carry signal as it is successively transferred to high order stages. To take a specific example, suppose that in a twenty digit computer the number present in the accumulator master rank comprises two zeros followed by eighteen ones Suppose the number to be read into the input register comprises nineteen zeros followed by a one If the adder-subtracter is set to add, a fraction of a microsecond after the introduction of the numberV in the input register the rst and second highest order adder-subtracter stages will indicate a sum of Zerofand a carry of zerof The next seventeen stages will indicate a sum of one and a carry of zerof However, the lowest order stage will indicate a sumjof zero and a carryof one The carry of one from the lowest order stage will reset the next higher -order stage to that the number of gate circuits required increases very rapidly asthedigital capacity of the computer is increasedV so thatit becomes impractical to employ such yan arrangement in computers having a capacity of more than a few digits, for example ve lor ten digits. Also, combined adder-subtracter stages may require much moreY equipment than either an adder ora subtracter circuit. Y Y

Other proposals have been made to arrange the stages in groups with simultaneous carry withinl groups and serialcarry between groups in order to effect a compromise between ripple propagation time and equipment requirements. Vln-this arrangement the carry ripple'time is proportional'to they number of groups employed. If a small number of groups are employed in4 order to reduce rippleV time the equipmentrequired y.in each group is quite large. If allarge number of groups are employed in order to conserve equipment, the ripple time will stillV beY undesirably long.

The present invention overcomes these disadvantages of the prior art by arranging the adderstages, subtracter stages or combined adder-subtracter stages in groups of preselected size, and by 'providing for the simultaneous initiation of thecarry ripple in each-of the groups.` The' carry propagation within groups may beserial or simultaneous as desired. v l A' Therefore it is an object of the present invention to provide a relatively simple adder-subtracter circuithaving a relatively short ripple time.`

In particular, it is anrobvject ofrithe invention to pro-` are achieved by arranging the stages in groups. Stages in each group except the lowest order group are arranged to provide dual signal paths. The arrangement of the circuits of each path is such that there is an apparent carry of one supplied to the lowest order stage of one path of each group, and an apparent carry of Lzero supplied to the lowest order stage of the other path ofV each group. Each group provides a first sum and a first carry from the path having a carry of zero supplied thereto, and a second sum and a second carry from the path having a carry of one supplied thereto. A gate circuit associated with the carry output of each group determines the carry and sum pair which will be gated out of the following group to the utilization circuit. The carry ripple starts simultaneously in all groups and the total ripple time is approximately that of the longest group in the adder and/or subtracter circuit.

For a better understanding of the invention together with other and further objects thereof reference should now be made to the following detailed description which is to be read in conjunction with the accompanying drawings in which: i

Fig. 1 is a block diagram of a preferred embodiment of the present invention;

Fig. 2 is a circuit diagram of a two stage addersubtracter chain which may be employed in the circuit of Fig. l;

Fig. 2A is a modification of a portion of the circuit of Fig. 2;

Fig. 3 is a circuit diagram of one preferred form of gate circuit employed between adjacent groups in the circuit of Fig. l; and

Fig. 4 is a circuit diagram of a preferred form of adder-subtracter circuit which combines the two signal pathsinto a single circuit.

Fig. 1 shows the adder-subtracter circuit ofthe present invention connected to registers 12, 14 and 16 which may serve as an input register, an accumulator slave rank and an accumulator master rank, respectively. In the arrangement shown in Fig. l the adder-subtracter circuit has one group of input leads 12a*12d connected to register 12, a second group of input leads 14a-14d connectedV to register 14 and a group of output leads 16a-16d connected to register 16 through lgates 15a-ld, respectively. Gates 18a-18d are controlled by a signal on conductor 19. Typically the adder-subtracter of Fig. l wouldvreceive the addend or subtrahend from the register 12, the augend or minuend from the register 14, and supply the sum or difference to the register 16. The final carry or borrow signal of the adder-subtracter is supplied by or gate 20. In a typical computer, register 12V might comprise a plurality of independent bi-stable circuits, such as Eccles-Jordan trigger circuits, together with appropriate gates for clearing Vthe register and for reading in information from some external source, for e:- ample a memoryl section o f the computer. The clearing circuits and input gates are not shown in Fig. 1 since they do not form a part of the present invention. Similarly, registers 14 and 16 may each comprise a like plurality of bi-stable circuits together with appropriatel transfer gates and clearing circuits. `In a typicalrcornputer a plurality of sets of transfer gates would Ybe provided between registers 16 and 14. One set o f gates might transfer the data in register 16 to register 14 with a one digit left shift. A second set might accomplish the transfer with a one digit right shift. Again these gates have not been shown in Fig. 1 since they do not form a part of the present invention.

In the description which follows it is assumed that registers 12, 14 and 16 each have Va capacity ofiifteen binary digits. It is also assumed that the adder-subtracter has a capacity of fifteen binary digits and that the circuits for accomplishing'the addition and subtraction are arranged in four groups, namely-groups-21,22, 2?; and 2,4. Each of the groups 22, 23 and 24 comprises 4 two adder-subtracter circuits 22a-2217, 23a-23b and 24a-24h. Each of the circuits 22a, 23a and 24a may be a conventional adder circuit having a capacity of a few digits, typically 3, 4 or 5.

Fig. 2 illustrates a two stage adder-subtracter of the type which may be employed in group 21 and in circuits 22a, 23a and 24a of groups 22, 23 and 24. The circuits 22b, 2311 and 2417 may be similar to the circuit shown in Fig. 2 except the lowest order stage may be modied as shown in 2A.

lt should be understood that the present invention is not to be limited to the number of groups shown or to the digit capacity of each of the groups which may be mentioned from time to time. It lies within the scope of the invention to provide as few as two groups or as many groups as there are digits in the numbers to be added or subtracted. The digit capacity of each group may vary Afrom one to one less than the total number of digits. However, as the description which follows will indicate, it is generally preferable to employ more than the minimum of two groups, each group including a small but not necessarily equal number of individual addersubtracter stages.

The bi-stable circuits in input register 12 registering the lowest order digits of the addend or subtrahend are connected to group 21 by way of connection 12a. It was assumed above that the circuits of group 21 had a capacity of three binary digits. Therefore connection 12a will include three conductors or three pairs of conductors, each conductor or each pair of conductors connecting one of the three lowest order stages of register 12 to a corresponding adder-subtracter stage in group 21. Signals representing the three lowest order digits of the augend-minuend are supplied to group 21 by way of connection 14a. Again, connection 14a will include three conductors or three pairs of conductors but it is represented by a single line in the interest of simplifying the drawing. In a binary system the only digits that must be represented are zero and one Therefore it is convenient to employ an on-o type signal. ln the description which follows it will be assumed that an input is energized or that a signal is present at an input if the potential of the input is other` than ground. Conversely an input is not energized or a signal is not present at an input if the potential of the input is substantially at ground potential.

A signal on add lead 32 conditions group 21 to provide three outputs signals representingthe three sum digits to connection 16u. These three signals follow separateY paths through and gate 18a to the three lowest order bi-stable circuits in register 16. The numeral 3 within the triangle representing and gate 1S@ indicates the three separate paths. A signal on subtract lead 34- conditions group 21 to provide three signals-by the same path, the signals this time representing the difference obtained by subtracting the three lowest order digits present in one of registers 12 and 143 from the three lowest order digits present in the other of these two registers. The` circuits of group 21 also supply a signal on lead 36 if the final carry `or borrow resulting from-the addition or subtraction of the three digits register 12 to or from the three digits in register 14 is a zero. A signal appears' on lineV 38 if the final carry or borrow is a one.

As mentioned earlier, each of the higher order groups comprises two adder-subtracter circuits, each circuit including `one or moreV adder-subtracter stages. En group 22 the first circuit is represented by block 22a and the second circuit is represented by block 22h. `Circuits 2211 and 22b are each connected to the same group of lai-stable circuits' in register 12 by way of multiconductor connections 12b. VIn the'discussion which follows it will be assumed that circuits 22a and 22b have a capacity of three binary digits and hence are Aconnected tc three bi-stable circuits .in register12. Similarly, circuits 22a and 2215 are' connected to three bi-stable circuits in register 14 by way of multiconductor connections 14b. Circuits 22a and 22b are each connected to add lead 32 and the subtract lead 34. The arrow 40 associated with circuit 22a schematically represents that the lowest order stage of this circuit is so arranged that an input carry of zero is represented in the carry and sum or borrow and difference output signals of this rlowest order stage. It should be understood that in an actual circuit it will not be necessary to supply a signal indicating a carry of zero, In a binary adder stage the logic may be selected to represent either an input carry or borrow of one or zero as long as the value remains iixed. Similarly, arrow 42 associated with circuit 22h schematically represents thatthe lowest order stage of this circuit is so arranged that an input carry of one is represented in the carry and sum or borrow and difference output signals of this circuit. Thus circuit 22a can be set to provide an output signal which represents the sum of digits 4 to 6 of register 12 and the digits 4 toV 6 ofv register 14`assuming that, in the normal addition of the binary numbers present in register 12 tothe number present in register 14, no carry.

would take place from the third column to the fourth column. Similarly, circuit 22b would be set to provide the sum of the same digit groups but on the assumption that a carry would take place from the third column to the fourth column. Only one of these sums will be correct for the numbers actually registered in registers .12 and 14. The advantage of providing the two circuits is that the assumed carry signals are -available as soon as the circuit is programmed to add. These assumed carry. signals do not depend at all on any carry ripple prop.

larly, circuit 22h supplies a three-digit partial sum orV difference signal to multiconductor connection 50 and a carry or borrow signal to conductor 52 or conductor'54.r

Connections 46, 48, 52 and 54 represent single conductors or single signal paths. However, connections 44 and 50 represent three groups of conductors, one for each digit in the sum -or difference.

And gate 56 has the inputs thereof connected to connection 44 and conductor 36. Therefore and gate 56 will provide three separate output signals provided conductor 36 is energized. As mentioned earlier, conductor 36 will be energized if the'carry or borrow signal supplied by group 21 represents a zero. The output lof gate circuit 6 is connected through or buffer 58 and gate circuit 18b to the appropriate bi-stable cir-Y cuits in register 16. Similarly, a three-digit lsum or diiferf ence signal present on connection 50 is suppliedV to an and gate circuit 60. Again gate circuit 60 is capable of separately handling a three-digit signal. A second input of and gate 60 is connected to conductor 38 from group 21. The output of gate 60 is connected to the Circuit 23b provides sum or difference signals on multi-i conductor connection 68, and carry signalsY on leads 70 and 72. The sum or difference signals from circuit 23a are supplied to register 16 through and gate 74, or buffer 76 and and gate 18C. The connection from gate 18e to register 16 is to the seventh to the tenth bi-stable circuits in this registen Similarly, the sum or difference signals from circuit 23b are supplied by way of and gate 78, or buffer 76 and and gate 18C to the same four bi-stable circuits in register 16. The gatingvof the sum or difference signals to register 16 is similar to the gating of the sum or difference signals from circuits 22a and 22h except that one additional variable has been added. Instead of two possible carry signals for controlling the gating of these sum or difference signals there are now four carry signals, two each from circuits 22a and 22b. The operation of gates 74 and 78 are controlled by signals received from or buffers 80 and 82, respectively. yEach buffer has two inputs. The first input of buier 86 is received from and gate -84 and the second from and gate 86. And gate 84 has its two inputs connected toconductors 46 and 36. kTherefore this gate will provide an output signal if the sum or difference of digits four to siX is gated out of 22a and if the carry or borrow of circuit 22a is zero. And gate 86 has its two inputs connected to conductors 52 and 38. Therefore and gate 86 will have an output signal if the sum or difference of digits four to six is gated out of circuit 22b and if the carry or borrow of circuit 22b is a zero. It should be noted that in each case the carry or borrow signal from the preceding group has to be zero before the sum or difference is gated out of circuit 23a. This carry of zero corresponds to Vthe assumed carry `of zero represented by the arrow 88 associated with circuit 23a. Or buffer 82 has its two inputs connected to and gates 9@ and 92, respectively. And gate 90 is supplied with signals by conductors 48 and 36. And gate 92 is supplied with signals from conductors 54 and 38. Therefore or buffer 82 will have an output signal if the selected circuit in group -2'2 has an output carry of one. The means employed for gating the from circuits 24a and 24h to register 16 `are similar to those associated with circuits 23a and 23h. The only difference lies in the fact that and gates 94 and 96 and or buffer 98 must be capable of handling a fivedigit sum or difference signal rather than the three-digit sum or differencesignal handled by and gates 56 and 66 and the four-digit sum or difference signal handled by and gates 74 and 78.

The digital capacity ofthe adder-subtracter may be increased by adding groups similar to groups 22 or 23,

or by increasing the digital capacity of one yor more of the groups. There is no definite limit on the number of stages which may be included within each group, but proper selection of the relativenumber of stages within the several groups Will result in the proper sum being gated from all groups to register 16 at the same time. It-

can be shown that this arrangement will give the minimum possible carry ripple time with a circuit of the present invention.

It should be noted thatthe carry outputs of group 21 and circuits 22a, 22b and 23a and 23b are employed only in gating circuits within the adder-subtracter. It is' not necessary to employ these carry. or borrow signals as data because each succeeding group initiates a new carry or boirow signal for each of the two circuits in the group. However, in the iinal group of the adder-subtracter, in this case group 24, it may be desirable to provide an in- -dication of the final carry or borrow signal resulting from the addition or subtraction of the number in register 12 and the number in register 14. Therefore conductor Nil from circuit 24a is connected to one input of an and gate 102. Lead 106B is energized if the carry or borrow signal from circuit 24a represents a one. The second input 104 is connected to the output of or bufer 166. Or buffer 106supplies a signal if the carry `or borrow signal of the selected circuit in group 23 is a zero. It will be remembered that la carry of zero in group 2.3 selects a sum or difference signal from circuit 24a in group 2.4- .Similerln a Connettiti@ .is made by Wwf,

conductor 168 from circuit 24b to one input of an and gate 11i?. Lead 108 is energized if the carry or borrow output of circuit 24h is a one. A second input of and gate 110 is connected by way of conductor 112 to the output of an or buifer 114. r butter 114 provides an output signal if the output carry of the selected circuit in group 23 is a one. Therefore the output of or gate 2t?, which receives the output signals of gates 102 and 110, will be energized if the carry or borrow signal in the selected circuit of group 24 is a one. it will not be energized if the carry or borrow signal in the seiected chain is a zero, The circuit for gating out the carry of one in group 24 may be duplicated to gate out a carry of zero from circuits 24a and 24b. However, this is not usually necessary since a carry of zero is indicated by the absence of a carry of one, that is, by the absence of a signal from or butter 20.

Fig. 2 illustrates a two stage adder-subtracter circuit of the type which may be employed in group 21 and in adder-subtracter circuits' 22a, 23a and 24a. Only two stages are shown in Fig. 2 since additional stages in the circuit would merely duplicate the left hand stage of Fig. 2, that is, the portion of the circuit to the lett of broken line 1312*. The right hand stage of Fig. 2 has input leads 124- and 126 which may be connected to the first, fourth, seventh or eleventh bi-stable circuit of register 12. That is, if the circuit of Fig. 2 illustrates' the single adder-subtracter circuit of group 21, conductors 124 and 126 would be connected to the `1rst or lowest order oi-stable circuit in register 12. lf the circuit of Fig. 2 is tal-:en to represent the circuit in 22a, then conductors 124 and 126 would be connected to the fourth oi-stable circuit in input register 12, again counting from the lowest order stage; 1n this case conductors 124 and 126 would form one pair of the three pairs of conductors represented by the connection 12b of Fig. 1. Conductor 124 will be energized if the bi-stable circuit in register 12 is registering a one. Conductor 126 will be energized if the bi-stable circuit is registering a zero. Conductors 1 3 and 130, which correspond to one pair of the three pairs of conductors represented by the connection 14h of Pig. l, are provided for receiving the corresponding digit from register 14. Again conductor 128 will be energized if the bi-stable circuit in register 14 to which it is connected is representing a one, Conductor 1311 will be energized if this bi-stable circuit is registering a zero. The right hand stage `of Fig. 2 may be divided into two parts. The part to the left of broken line 132 generates the sum or diiierence digit which will be supplied to register 16. The portion of the circuit to the right of broken line 132 generates the carry or borrow digits which are supplied to the left hand stage of Fig. 2. No input carry signal is supplied to the right hand stage of Fig. 2 but the circuits are so arranged that the sum and carry outputs are those which would be present if a carry or borrow of zero were present. 1n group 21 the input carry or borrow will always be zero since there are no lower order digits to provide a carry or borrow signal to this group. Circuits 22a, 23a and 24a are so arranged that a carry of zero is assumed even though there are lower order digits which, in a conventional computer circuit, might provide a carry other than zero.

In Fig. 2, the bases of transistors 134 and 136 are connected to conductor 124, while the base of transistor 138 is' connected to conductor 126. Conductor 123 is connected to the bases of transistors 1411 and 142, and the second conductor 13) from register 14 is connected to the bases of transistors 144 and 146. Conductors 149 and 151, which connect to the bases of transistors' 143 and 159, respectively, are the subtract and add program conductors, respectively. Conductors 149 and 151 correspond to conductors 34 and 32 of Fig. l. In the circuit of Fig. 2, a sum of one is indicated if conductor 154, which is connected to one end of resistor 152, is at a potential other than substantially groundV potential, and

a sum yof zero is indicated if this conductor is at or near ground potential. To accomplish this result the end of resistor 152 remote from conductor 154 is connected to a source of supply potential schematically represented by the symbol Vcc PNP transistors and negative signals and supply potentials' are assumed throughout this description, but it should be understood that other types of transistors or other forms of circuit elements, such as magnetic cores, neon tubes or the like, may be substituted therefor without departing from the scope of the invention.

The end of resistor 152 associated with conductor 154 is returned to ground through two parallel paths, one path being the emitter-collector paths of transistors 134 and connected in series, and the second path being theemitter-collector paths of transistors 138 and 144- connected in series. 1t will be recognized that this forms a conventional portion of an adder-subtracter stage in which the four transistors are employed like on-oif switches, the circuit between emitter and collector being substantially a short circuit if the conductor connected to the base is energized and substantially an open circuit if this conductor is not energized.

In the circuit of Fig. 2 a carry or borrow of zero is indicated if the lower end of resistor 156 is at a high potential. Again this is accomplished by returning one end of resistor 156 to the supply potential and connecting the other end to ground through two parallel paths comprising, respectively, fthe emitter-collector paths of transistors 148, 146 and 136 in series and the emittercollector paths of transistors 150, 142 and 136 in series. It should be noted that transistor 136 is common to these two paths. The parallel combination of the emittercollector paths of transistors 148 and 146 and the emittercollector paths of transistors 142 and 150 are required since the carry digit resulting from the addition of two digits is not always the same as the borrow digit resulting from the subtraction of the same two numbers. The fact that no transistor in the carry-borrow portion of the circuit is connected to conductor 126 indicates that the carry or borrow digit will always be zero if the input carry is zero and the digit from register 12 is zero It should be noted that it is not necessary to provide transistors controlled by the add conductor 151 and/orl the subtract conductor 149 in the left hand portion of this iirst` stage since in binary arithmetic the sum digit resulting from the addition of two or more digits is the same as the difference digit resulting from the subtraction of these digits.

A signal representing a carry of one is generated by connecting the lower end of resistor 156 to the input of an inverter stage including transistor 15S. Thus conductor 1611, which is connected to the output of the inverter, will be at a high potential if the carry or borrow digit is one 1t should now be clear that the digit is a borrow digit if the subtract lead 149 is energized and that it is a carry digit if add conductor 151 is energized. Conductor 162, which is connected to the input of the inver-iter, that is to the lower end of resistor 156, will be energized, i.e. will be at a potential other than ground, if the carry or borrow digit is a zero The left hand stage of Fig. 2 is similar to the stage just described except that it is made slightly more complex by the fact that the carry or borrow from the right hand stage may be either a zero or a onef Conductors 164. and 166 of Fig. 2 connect to the second, fifth, eighth or twelfth bi-stable circuit in input register 12. These lai-stable circuits are the second lowest order stages in each of the groups. Conductors 168 and 176 connect to the corresponding bi-stable element in register 14-that is, if conductors 164 andk 166 connect to the fifth bi-stable element in register 12, then conductors 16d and 17@ connect to the iifth bi-stable circuit of register 14. in this case conductors 164 andl 166 would comprise a secondi pair of thethree pairsy of .gg conductors represented by connection 12b, the first pair being conductors 124 and 126, and conductors 16S and 176 would comprise a second pair of the three pairs of conductors represented by connection 14h. Conductors 166 and 170 will be energized if the digits registered by `the bi-stable circuits to which they are connected are one Conductors 164 and 16S`willbe energized if the respective digits are zeros sum or difference of one is indicated by a high potential on output conductor 172. A carry or a borrow of one is indicated by a high potential on conductor 174, and a carry or a borrow of zero is indicated by a high potential on conductor 176. A high potential will be present on each of these conductors by reason of their being connected to a source of supply potential through the resistors 180, 182 and 184, respectively, unless a path is completed from one or more of these conductors to ground through the transistor network. Conductors 174 and 176 may connect to additional addersubtracter stages in the same manner that conductors 16@ and 162 are connected to the left hand stage of Fig. 2. If the left hand stage of Fig. 2 is the last stage of one of the adder-subtracter circuits of Fig. 1, the signals appearing on conductors 174 and 176 are not employed as carry signals but are employed as gating signals for gating out the sum or difference of the following addersubtracter circuit. For example, in group 21,A conductor 174 would correspond to conductor 38' of Fig. `1 and conductor 176 would correspond to conductor 36 kof Fig. l. The operation of the left hand stage may be understood by tracing the various paths to ground from conductors 172, 174 and 176. For example, one path to ground from conductor 172 is by way of transistors 1S6, 188 and 190. ductors 162, 168 and 164, respectively. Thus digits of zero from register 12 and register 14 and a carry or borrow of zero from the right hand stage produce a sum or difference of zero at conductor 172.

Y The adder-subtraoter chains 22h, 23b and 24h of Fig. l may be made up of stages, all of which are similar to the left hand stage of Fig. 2, provided the carry one input to the lowest order stage is permanently energized by connecting it to a source of supply potential. This would introduce the assumed carryV of one represented by arrow 42 of Fig. 1. However, the same result can be achieved with considerable saving in circuitry by slight modification of the right hand stage of Fig. 2.Y

The modied right hand stage is shown in Fig. 2A. Parts in Fig. 2A have been given the prime numbers of corresponding parts in Fig. 2. The portion of the circuit to the left of broken line 132 is similar to the corresponding circuit in Fig. 2 except that the connections to the bases of transistors 140 and 144' have been reversed. Note that in Fig. 2 the base of transistor 140 is connected to conductor 128;. In Fig. 2A the base of transistor 140 is connected to conductor 130'. Similarly, in Fig. 2 the base of transistor 144 is connected to the conductor 136. In Fig. 2A the base of transistor 144 is connected to conductor 128. It can be shown that the signal present on conductor 154 of Fig. 2A will be the proper signal to indicate the sum or difference of any combination of binary digits in registers 12 and 14 and a carry or borrow digit of onef In the circuit to the right of broken line 1312 the only change that is required is the connection of the base of transistor 136 to input conductor 126' instead ofconductor 124', and the addition of a transistor 20) which provides a third path from the lower end of resistor 156 to ground. Again it should be remembered that conductors 126 and 124 form one pair of the three pairs of conductors represented by the connection 12b of Fig. 1. The base of transistor 200 is connected to input conductor 124'. It can be shown that a carry or borrow digit will always be present if the digit in the input register is one and a carry or borrow digit of one is present from the preceding stage. Therefore ln the left hand stage a` These transistors are energized by condigits in registers 12 and 14 and a carry digit of one."

Conductors 160 and 162 of Fig. 2A connect to the succeeding stages in exactly the same way as the corresponding conductors in Fig. 2.

The circuits shown in Fig. 2 and Fig. 2A may be set to add or subtract as desired. If only addition is required the circuits may be simpliiied by eliminating all transistors energized by the subtract program conductors 149 and all other transistors in paths which must be completed through these subtract transistors. For example, in Fig. 2 transistors 148 and 146 may be removed but not transistor 136 since a path may be completed through this transistor and transistors 142 and 150. Transistor 150 may be replaced by a permanent connection between resistor 156 and the collector 142 since the circuit is now always programmed to add. If` only subtraction is to be performed, the paths involving the transistors energized by the add program conductor 151 may be removed and the transistors energized by the subtract program conductor 149 may be replaced by permanent connections.V

Fig. 3 is a circuit diagram of the gating circuits connecting adder-subtracter circuits 22a and 22h to addersubtracter circuits 23a and 23h of Figi. As shown in Fig. 3, gate circuits 56 comprise three transistors, 56a, 56h and 56e, the bases of which are energized in parallel from conductor 36. Similarly, gate circuit 60 comprises three transistors, 60a, 6011 and 60C, the bases of which are energized in parallel from conductor 38. In Fig. 3,

Y and gate 84 comprises the transistors 84a and 84b in The series combination of these two transistors provides the desired and function.` And gate 86 is formed by transistors 86a and 3611 in series. The collectors of transistors 64a and 86a are returned to a source of supply potential represented by the symbol -Vcc through a load resistor 194). And gate 90 comprises the transistor 96a and transistor 841: in series combination. Y Note that the single transistor 84b takes the place of the two connections from lead 36 to the and gates 84 and 90 of Fig. 1. And gate 92 comprises transistor 92a and transistor 86b in series. The collectors of transistors 92a and 90a are returned to the supply potential through load resistor 192. The function of or gate is performed in Fig. 3 by the common connection Sil between the collectors of transistors 34a and 86a. Conductor 80 is connected to the base of a transistor 194. This transistor and resistor 196 together form a buffer stage. The output of the buffer stage including transistor 194 is connected to the bases of the four transistors 74a- 74d making up and gate 74. A second transistor 198 series.

is energized by conductor 82 which performs the func-v tion of the or gate 82 shown in Fig. 1. This buffer stage is completed by a load resistor 200. Buffer stage 19E-200 controls the operation of transistors 78a-78d which form and gate 78.

The circuit of Fig. 3 operates in the following manner. The transistors making up gate circuits 56 and 60, for example, will act as a high impedance in the absence of a signal on Ithe bases thereof. Either conductor 36 or conductor 38 will be energized depending upon the carry signal supplied by group 21 of Fig. l. If conductor 36 is energized, the three transistors 56a-56c making up gate 56 will appear as a very low impedance, thereby permitting any signal which may be present on one of the leads from adder-subtracter circuit 22a to be communicated to the associated bi-stable circuit in register 16. Similarly, if conductor 38 is at a high potential indicating a carry signal of one in the output of group 21, the transistors 60a-60c in gate circuit 60 will appear as a lowimpedance thereby permitting any signals present on the conductors 154', 172', etc. of circuit 2217 to be communicated to the corresponding bi-stable circuits in register 16. The proper sum from group 23 is selected in the following manner. Suppose conductor 36 is energized, thereby selecting the sum from group 22a. The high potential on conductor 36 will cause transistor $4!) to appear as a low impedance. The base of only one of the two transistors 84a and 90a will be energized by a signal from the carry output of group 22a. Suppose for example that the carry output of group 22a is a one so that conductor 48 is energized. The signal on the base of transistor 93a will cause it to act as a low impedance. Therefore a circuit is completed from ground through transistor 34h and transistor 90a to the resistor 192. This connection will cause the lower end of resistor 35.32 to assume a potential only slightly above ground potential. The low potential at the lower end of resistor' 192 will cause transistor 198 to be cut on. The collector of transistor 198 will be at a high potential since it is returned to the supply potential through resistor 2%. The high potential at the collector of transistor E32 will supply a high potential to the bases of the transistors 7de-'78d making up gate 78. This will permit the output signal of circuit 2317 to be supplied to register i6. it should be noted that if conductor 36 is at a high potential, conductor 38 will be at a low po-V tential. A. low potential on the base of transistor 86b will cause .this transistor rto act as a high impedance. Therefore the lower end of resistor 19@ will be at a high potential since the path to ground through transistors 8de and 36h is blocked by the high impedance of the latter transistor. The parallel path through transistor 54a and transistor t-/b is blocked by the high impedance of transistor 84a resulting from the absence of a zero carry signal on conductor 46. The high potentiai the lower end of resistor 1% is supplied to the base of transistor 194 causing this transistor to conduct. Conduction through transistor M4 drops the potential of the lower end of resistor 196 to a value near ground. This low potential causes transistors in gate circuit 742 to be cut oi, thus blocking the sum signal from addersubtracter chain 23a. The other three combinations of carry signals from group 2l and carry signals from` adder-subtracter circuits 22a and 22h may be traced through the circuit in a similar way.

The above description of Figs. 2, 2A and 3, which are detailed circuits of the parts of the circuit shown in Fig. l, also serves as a description of the operation of Fig. l. The gating circuit of Fig. 3 is merely duplicated between groups 23 and 2d or, in general, between all adjacent groups in the complete adder-subtracter. Thereforev the capacity of the adder-subtracter may be increased by adding more groups similar in nature to groups 22 and 23. Adding groups in this manner will not cause any appreciable increase in the carry ripple time since the carry propagation in the two paths of the new groups will start simultaneously with the carry ripples in all other groups. Each added group will increase the over-all carry time by approximately the carry ripple time for one digit. Also the addition of the new groups will not require any alteration in the other groups since each group is independent of all other groups except for the g.. Thus the circuit shown in Fig. l is ideally suited to a unit type circuit construction in which the capacity may be increased as the occasion demands by adding one or more prewired units of the appropriate type. A prewired unit :would include two adder-subtraoter circuits corresponding to circuits 22a and 22h for example and a series of gate circuits corresponding to gate circuits 56, S0, gli, Siti, SS, 82, Se, 92, and 6d of Fig. l. The added unit may he arranged to add 3, 4, or more digits as desired. It is also possible vto increase the capacity of the addersubtracter circuit' by replacing one or more of the groups of4 Fig. l with anew group having a greater or lesser number of stagesin each. circuit. This will havea direct gating si Un als received from preceding groups.

eiect on the ripple time but it will have no eiect on the operation of the other groups.

The addition or subtraction step is complete when all sums or differences have been gated into register 16. The time duration of the carry ripple in each group is proportional to the number of stages in that group. The sum or diierence is available for gating into register 16 as soon as this carry ripple is completed. However, the sum or difference cannot be gated out of group 24, for example, until the decision is made on which sum or diierence and carry or borrow are to be gated out of group 23. This is so because the carry or borrow output of circuit 23a may be different from the carry or borrow output of group 23'0. This will result in a minor decision ripple starting with group 22 and proceeding to group 24. The time duration of this decision ripple will be proportional to the number of groups employed and may be approximately equal to the carry or borrow ripple of a conventional adder-subtracter circuit having a nurnber of stages equal to the number of groups. Thus it is possible to minimize the overall ripple time by employing a relatively small number of stages in the less significant groups, thus permitting the decision ripple to start at the earliest possible moment. The groups handling the more signiiicant digits may have a greater number of stages since the sum or difference signal is not required of these stages until the completion of the carry ripple in the earliest group plus the completion of the decision ripple to the later group. It is for this reason that groups 21, 22, 23 and 24 are shown in Fig. l as comprising 3, 3, 4 and 5 stages, respectively. The overall ripple time of the l5 digit adder-subtracter of Fig. l is of the order of the ripple time of a six digit adder of conventional design. The maximum ripple comprises Va three digit carry ripple in adder-subtracter 21 and three unit decision ripple in gates 56-6tl, 74978 and 94-96- Therefore the ripple time has been cut by a factor of 2.5. This factor would be of the order of four for a forty digit adder-subtracter constructed in accordance with the principles of the present invention.

The circuit of Fig. 4 combines the two adder-subtracter circuits of a group into a single circuit with a net saving of circuit components. Again in Fig. 4 only two stages have beeny shown since all stages except the lowest order stage in a group are identical. The lowest order stage is somewhat simpler than the higher order stage or stages since the carry input signals to Ithis stage are fixed. In Fig. 4 the two stages are separated by the broken line 220, the lower order stage being the one on the right.

The righthand stage of Fig. 4 may be divided into two parts, the part to the right of broken line 222 providing the sum or difference signals and the part to the left of line 222 providing the carry or borrow signals. In the portion of the circuit to the right of line 222 transistors 224, 226, 228 and 23d are connected so as to provide two alternative paths to ground from the lower end of resistor 232; One path is through the emitter-collector paths of transistors 224 and 226 in series, and the other path is through the emitter-collector paths of transistors 228 and 23? in series. The other end of resistor 232 is returned to a source of supply potential represented in Fig. 4 by the symbol -Vcc. Therefore the lower end of resistor 232 will be at a high potential unless one of the two paths mentioned above provides a low impedance path to ground. Conductors 234 and 236 extend to a single bi-stable circuit (not shown) in a register corresponding to register 12' of Fig. 1. Conductor 234 will be energized if the digit stored by this bi-stable circuit is a zero and conductor 236 will be energized instead if the digit is a one Conductors 238 and 240 are associated with a corresponding bi-stable circuit in a register corresponding to register i4 of Fig. l. Conductor 238 is energized if the digit registered by the bi-stable circuit is a zero and conductor 240 is energized if this digit is a one The bases oftransistors 224, 226, 228 and The lower end of a second resistor, 242 isconnected,

to ground through two parallel paths, onepath comprising 'the series combination of the emitter-collectorpaths of transsistors 244 and 230 in series, and the other comprising the emitter-collector paths of transistors 246 and 226 in series. The bases of transistors 244 and 246 are connected toL conductors 238 and 240, respectively. It can be seen from an inspection of Fig. 4 that the lower end of resistor 242 will be at a low potential if one digit on the two sets of input leads 234-236 and 23,8-240 is one and the other is zero, that is, if the binary sum or difference of the two digits is one However, this is equivalent to saying that the lower end of resistorV 242 will be at a low potential if the sum of the two input digits plus a carry of one is equal to zero since a sum of one plus a carry of one is zero with a carry of one Therefore the circuit just described is arranged to provide a high potential at the base of transistor 248 if the sum of the input digits plus a carry of zero is one, and to provide a high potential at the base of transistor 250 if the surn of the input digits plus a carry of one is fone. Output conductor 252 is connected to ground through the serially connected emitter-collector paths of transistors 254 and l248.V Conductor 256, which connects with the base of transistor 254, may connect to the carry equals zero conductor of the preceding group, for example conductor 36 or the output of or buffer 80 of Fig. 1. The bistable circuit (not shown) associated with conductor 252 may be so arranged that it is set to register a one if conductor 252 is at or near ground potential. Thus transistors 248 and 254 perform the function of one of the and gates in circuits 56 or 74, for example, of Fig. l. Similarly, output conductor 258 is connectedr'to ground through the serially connected emitter-collector paths of transistors 260 and 250. The base of transistor 260 is connected to conductor 262 which is energizedV by the carry equals one output of the preceding group. 'Ihus transistors 250 and 260 perform the function of one of the and gates in circuits 60 or 78, for example, in Fig. l.

The portion of the rst stage to the left of brokenV line 222 generates the four possible carry signals, i.e. a carry of one or zero assuming an input carry of zerofand a carry of zero or one assuming that the input carry is a one In this portion of the circuit one end of resistor 270 is connected to a source of supply potential represented by the symbol -Vca The other end of this resistor 270 is connected to ground through three parallel paths. One path comprises the emittercollector paths of transistors 271 and 272 in series, the second path comprises the emitter-collector path of transistors 273 and 275 in series ,and the third path comprises simply the emitter-collector path of transistor 274.

A high potential at the lower end of resistor 270 indicates a carry or borrow of zero, assuming an input carry of one Conversely a low potential at the lower end of resistor 270 indicates a carry or borrow of one, again assuming an input carry of onef It can be shown that, assuming an input carry or` borrow of one, a carry or borrow of one will always be present if the addend or subtrahend digit is one Therefore the base of transistor 274 is connected to input conductor 236. It is alsoY possible .to show that a carry of one will always be present if the augend digit is one Therefore the bases of transistors 271 and 272 are connected to the add program lead 284 and lead 240, respectively. If both the augend and addend digits are one there are two low impedance paths from the lower end of re- 14,' sistor 270 to ground, one through transistors 271 and 272 and thel other through transistor 274. This will have no efr'ect on the operation ofthe circuit since either one of the paths alone is a low impedance compared to resistor y270. Finally it can be shown that a borrow of one will always be present if an input borrow of one is assumed'and if the minuend digit is zero Therefore the bases of transistors 273 and 275 are connected to the subtract program lead 286 and to input lead 238. A carry equals one signal is generated by connecting the lower end of resistor 270 to the input of an inverter comprising transistor 278 and resistor 280. The carry equals one signal, if present, will appear on conductor 282 which is connected to the output of the inverter.

The remainder of the right hand stage is employed in generating a carry signal assuming an input carry of zero. This carry will be indicated by a signal on conductor 290 if it is a zero or on conductor 292 if it is a one Again conductor 290 is connected to conductor 292 through an inverter comprising transistor 294 and resistor 296. Since conductor 290 is to be at a low potential if the carry is a one, it is connected to the lower end of a resistor 300 which has its upper end connected to a source of supply potential again representedk by the symbol Vea The lower end of resistor 300 is connected to ground through two paths, one path comprising the emitter-collector paths of ltransistors 302, 304 and 306 in series and the other path comprising the emitter-collector paths of transistors 308, 310 and 306 in series. Again, each of these transistors will present a low impedance between emitter and collector if its base is energized but will present a high impedance if its base is not energized. The bases of transistors 302, 304, 306, 308 and 310 are connected 4to conductor 286, 238, 236, 284 and 240, respectively. Thus one path from resistor 300 to ground is completed if the subtract conductor 286 is energized, the minuerld digit is a zero, i.e. conductor 238 is energized, and the subtrahend digit is a one; i.e. conductor 236 is energized. The other path is completed if the add conductor 284 and conductors 236 and 240 are energized. Conductors 236 and 240 are energized if the two input digits are ones It can be shown that these two conditions are the only two conditions that will give an output carry or borrow of one if an input carry or borrow of zerof is assumed.

Th'evleft hand stage is similar to the right hand stage but more complex as a result of the two pairs of carry input signals from the right hand stage. In this stage the signal representing a sum digit of one with an assumed carry of zero from the preceding group appears at conductor 320. It should be remembered that the two stages of Fig. 4 are of the same ygroup and that the carry that is assumed is the carry output of the preceding group and not the preceding stage within a group. The carry output of the preceding stage within a group is communicated by a direct connection to the following stage. Conductor 322 is energized if the sum or difference digit is one for an assumed carry or borrow input of one Transistors 324 and 326 perform a gating function similar to transistors 248 and 254. Transistors 328 and 330 correspond to transistors 250 and 260 of the right hand stage. 'I'he conductors to the bases of transistors 326 and 330 have been numbered to correspond to the conductors connected to the bases of transistors 254 and 260 since they are energized from the same source. The lower end of resistor 332 is connected to ground through four paths, these paths comprise the serially connected emitter-collector paths of the following transistors:

Path l-Itransistors 334, 336 and 338 Path Z--transistors 334, 340 'and 342 .Path 3--transistors 344, 346 and 342 Path l--transistors 344, 348 and 338 Conductors 350 and 352 connect to the same register as conductors 234 and 236 but to the next higher order Transistor Conductor Resistor 363 connects conductor 322 to a source of supply potential. There are four possible paths from the lower end of resistor 363 to ground. These paths are through the serially connected emitter-collector paths of the following transistors:

Path -transisto-rs 362, 336 and 338 Path 6transistors 362, 340 and 342 Path 7-transistors 364, 366A and 368 Path S-transis-tors 364, 370V and 372 The conductors connected to the bases of the transistors in paths 5 through 8 are as shown below:

Transistor Conductor The carry or borrow output for an assumed carry input of zero appears on conductors 374 and 376. Conductor 374 is energized to indicate a carry output of one and conductor 376 is energized to indicateA a carry output of zerof Conductor 376 is energized byY ak connection to the lower end of resistor 373 which hasV itsupper end connected to a source of supply potential'. The lower end of resistor 373 is connected to ground through the following paths:

Path 9--transistors 389', 382, 348 and 338 iath lil-transistors 385), 382, 346'and 342 Path ll-transistors 380i, 384` and 386 It should'be noted that these three paths all include transistor 33t? which has its base connected to the subtract conductor 286. The lower end of resistor 378 is also connected to ground through the: following paths which include transistor 388" which has its base connected to the-` Transistor Conductor If any one of these paths is a low impedance, the lower end of resistor 378 and conductor 376 will be at a potential near ground indicating that no carry of zero is present, i.e. that a carry of one is present. The lower end of resistor 378 is connected to conductor 374v through the inverter comprising transistor 402 and resistor 494. Therefore, if conductor 376 is at a low potential', then conductor 374 will be at a high potential indicating `that a carry of one is present.

The carry or borrow output yfor an assumed carry of one appears on conductors 406 and 408. Conductor 406 is energized if the carry or borrow is a one and conductor 494 is energized if the-carry `or-iborrow digit-is a zero Conductor 468 is energized by connecting it to the lower end-of resistor 4M which has its other end connected to a source of supply potential.. The potential of conductor 468 is controlled by connecting the lower 16. end of resistor 410 to ground through: the following paths:

Path ISL-transistors 412,. 414, 366 and 368 Path l-transistors 412, 414',` 370 and 372 Path l7-transistors 412, 416 `and 418 All three of these paths include transistor 412' which has its base connectedv to the subtract lead 286.

The lower end of resistor 410 is also connected to groundy through the following paths, all of which include transistor 420 which has its base connected to the add conductor 284:

Path l8-transistors 420, 422 and 418 Path 19--transistors 420, 424, 394 and 396 Path ZO-transistors 420, 424, 398 and 490 The conductors connected to the bases of the transistors associated with resistor 410 are as follows:

Transistor Conductor The lower end of resistor 410` and conductor 408 will be at or near ground potential if any one of the paths associated therewith presents a low impedance as a result of a signal supplied to the bases of all transistors in that path. It is to be understood that as used in this specication the term low impedance means low or small in comparison to any resistor connected in series with the path, for example resistor 410. An inverter comprising transistor 426 and resistor 428 connects the lower end `of resistor 410 to conductor 406. This inverter causes conductor 406 to be at a high potential if conductor 408 is at a low potential and at a low potential if conductor points out, each stage receives an input from a bi-stable circuit in each of two registers. In the preferred form of the invention each input comprises two conductors one of which is energized to represent a zero and the other of which is energized to represent a one. However, a single conductor may be employed to transmit a signal representing one of these two values and the signal representing the other value may be developed by an inverter which has its input connected to the single conductor.

The circuit of Fig. 4 provides two sets. of sum or difference digits. Each stage contributes one digit to each set. One set of digits representsA the binary sum of the numbers registered by the bi-stable elements associated with thatV group. The other set represents this sum plus one or the difference minus one, that is, it is the sum or difference resulting from an assumed carry or borrow of one at the input of the group. Although only the first circuit of the group is arranged to take into account this assumed carry of one, its eiect is transferred to the higher order stages by the carry signals propagated from the lower order stages to the higher order stages. In Fig. 4 the firsty sum or. diiferenceis gated out by energizing conductor 256 which renders transistors 326 and 254 conductive. The second sum or difference signal is gated out by energizing conductor 262` which renders transistors 330 and 260 conductive. Since conductors 256 and 262 are energized by the zero carry and one carry outputs of the preceding. stageonly one of these conductors may be energized at a time.

The circuit of Fig. 4 is caused to add the numbers' ductors should be energized at a time. The circuits are' such that if conductor 284 is energized, a carry of one is assumed in a portion of the first stageand carry digits are propagated from the lower order stages to the higher order stages by way of conductors 276, 282, 290 and 292, for example. If conductor 286 is energized a borrow of one is assumed inthe first stage and a borrow ripple -is propagated through the same interstage connections that propagated the carry. As explained previously, no carry signal per se is transferred from adder-subtracter 21, for example, to adder-subtracters 22a and 22b. Instead, adder-subtracter 22a provides a signal representing the sum (or difference) of the fourth to the sixth digits of registers 12 and 14 with no carry (or borrow) input to the lowest signiicant digit column. If the actual carry output of adder-subtracter 21 is a one, the signal from adder-subtracter 22a will not represent a correct portion of the total outputsignal therefore this signal will be discarded. The discarding of this signal is accomplished in gate 56 which is blocked if the carry output of -adder-subtracter 21 is a one. Similarly, adder-subtracter 22b provides a signal representing the sum (or difference) of the fourth to the sixth digits of registers 12 and 14 with a carry (or borrow) input of one, Thus, if the adder-subtracter stage 22a provides an incorrect portion of the total sum signal, stage 22b must provide a correct portion of the total sum-signal since there are only two possible carry signals from adder-subtracter stage 21, i.e. either a zero or a one.

In the nal stage of a group, one of the two pairs of carry or borrow signals is blocked by appropriate gate circuits associated with conductors 262 and 256. These gating circuits may take the form shown in Fig. 3;

Again the combined adder-subtracter of Fig. l may be simpliiied to a dual path adder ora dual path subtracter in the manner described in connection with'the explanation of Fig. 2. Also, other combinations vof paths may be employed in adder circuits, subtracter circuits or combined adder-subtracter circuits without departing from the spirit and scope of the present invention. It also lies within the scope of the invention to replace the transistors shown in Fig. 4 with other known forms of switching elements and to provide any additional corttrol or biasing circuits as may be required by these switching elements. n

The circuits shown relate to binary adder-subtracter circuits. However, it lies within the scope of the invention to arrange adder-subtractersofy any other radix in the manner shown in Fig. 1. It will be remembered that the carry or borrow digits for any radix arestilllimited to the values zero and one. In the appended claims the Yterm adder-subtracter is used as a generic term covering adders and subtracters individually. VThe term combined adder-subtracter is employed to 'describe a circuit which will perform addition upon the application of an appropriate signal or subtraction upon the application of a different signal. The term carry-borrow signal is used as, a generic term encompassing a carry signal and a borrow signal, individually. The term result is employed as a generic term for a sum and a difference, individually. The hyphenated term sum-dierence is also employed as a generic term covering either a sum or a difference but not both at once.

While there have been described what are -at present considered to be the preferred embodiments of the invention, it will be apparent that various modifications and other embodiments thereof will occur to those skilled in the art within the scope of the invention. 'Accordingly I desire the scope of my invention to be limited only by the appended claims. f

What is claimed is:

l. An arithmetic computation circuit having ar shortened carry propagation time, comprising means for dividing each of two numbers into n corresponding digit vcombining eachidigit group of one number with" the assumed carry-borrow input of zero, a second plurality of means for simultaneously combining each digit group except the lowest order digit group of the said-first number with the corresponding digit group of the other number by the same selectedarithmetic operation and with an assumed carry-borrow input of one to each group, thereby to provide a first result signal and a carry-borrow signal for said lowest order group corresponding to the result signal and carry-borrow signal which would result from the performing of the same arithmetic function on the said lowest order portions of said two numbers, and to provide a first result signal and a corresponding carryborrow signal and a second result signal and a corresponding carry-borrow signal for each group except said lowest order group, one of said result signals and the corresponding carry-borrow signal being a portion of the resul-t signal and the corresponding carry-borrow signal which would result from performing the same arithmetic operation on said two numbers, an outputcircuit, means for supplying the result signal of said combining means for said lowest order group of digits to said output circuit, means responsive to the carry-borrow output signal of the combining means for the lowest order group for selecting the result signal and the corresponding carryborrow signal of the combining means of the next higher order group resulting from an assumed carry-borrow signal for the higher order combining means corresponding to the carry-borrow output signal of said lowest order combining means, means responsive to `the selected carryborrow signals of each of said combining means except said lowest order combining means for selecting the result signal and the corresponding carry-borrow signall of the next higher order combining means resulting from an -assumed carry-borrow signal of the higher order combining means corresponding to the selected carry-borrow output signal of the lowerorder combining means, Yand means for supplying said selected Vresult signals to said output circuit. t

2. A parallel adder circuit having a shortened carry propagation time, comprisingA means for dividing each of two numbers into n corresponding digit groups, at least one digit group in each of the two numbers including morethan one digit, a rst plurality of means for adding each digit lgroup of one number to the corresponding digit group ofthe other number withk an assumed carry input of-zero,k asecond plurality of means for simultaneously adding each digitl group except the lowest order digit group kof'thesaid iirst number to the Ycorresponding digit group of the other number with an assumed carry input of one to each group, thereby to provide a irst sum signal and a carry signal for said lowest order group correspondiing to the sum signal and carry signal which would result from adding the said lowest order portions of said two numbers, and to provide a rst sum signal and a corresponding carry signal and a second sum signal and a corresponding carry signal for each group except said lowest order group, one of said sum signals and the corresponding carry signal being a portion of the sum signal and the corresponding carry signal which would result from adding said two numbers, an output circuit, means for supplying the sum signal of said adding means for said lowestorder group of digits to said output circuit, means responsive to the carry output signal of the adding means for the lowest order group for selecting the sum signal and the corresponding carry signal of the adding means of the next higher order group resulting from an iassumedcarry signal for the higher order adding means corresponding to the carry output signal vof said lowest order adding means, means responsive to the selected carry signals of each of said adding means except said 'and the corresponding carry signaliof the next higher -order adding means resulting from an assumed 4carry signal ofthe higher order adding means corresponding Vto the selected carry output signal of the lower order adding means, and means for supplying said selected sum signals to said output circuit.

3. An arithmetic computation system comprising a plurality of computation circuits each arranged to perform -the same 4arithmetic function, said arithmetic function being a single arithmetic function chosen from the two arithmetic functions addition and subtraction, means for distributing signals indicative of the individual digits of Afirst and second numbers among said computation circuits, each of said numbers being divisible into a like plurality of partial numbers, at least one of said partial numbers having more than one digit, each of said computation circuits receiving signals representing a partial number taken from said first number and a corresponding partial vnumber taken from said second number, each of said computation circuits providing at a rst output connection signals indicative of the digits in the result of the performance of said function on the two paltial numbers supplied Ito said computation circuit, each of said computation circuits providing at a second output connection signals indicative of the carry-borrow resulting from the performance of said function, each of said computation circuits except the computation circuit receiving the lowest order partial numbers providing at a third output connection signals indicative of the digits inY the result of the performance of said function on the two partial numbers supplied to said computation circuit .and an input carryborrow of one, said last-mentioned computation circuits each providing at a fourth output connection signals indicative of the carry-borrow resulting from the performance of said function on the two partial numbers supplied thereto and an input carry-borrow of'o'ne, an output circuit, gate means connecting said first and third output connections of said computation circuits to said output circuit, said gate means being responsive to carry-borrow signals at said second and fourth output connections to permit the passage of the result signals from only a selected one of said first and third output connections of each computation circuit to said output circuit.

4. An improved combined adder-subtracter `system comprising a plurality of combined adder-subtracter circuits, means for distributing signals indicative of the individual ldigits of first and second numbers Vamong said circuits, each of said numbers being divisible into a like plurality of partial numbers, at least one partialA number from each of said iirst and second numbers including more than one digit, each of said circuits receiving signals representing a partial number taken from said rst number and a corresponding partial number taken from said second number, means for setting said combined adder'- subtracter circuits selectively to add or subtract, each of said circuits providing at a first output connection signals indica-tive of the digits in the sum or difference of the two partial numbers supplied to said circuit, each of said circuits providing at a second output connection signals indicative of the carry or borrow resulting from the addition or subtraction, respectively, of the two partial numbers supplied thereto, each of said circuits except the circuit receiving the lowest order partial numbers providing ata third output connection signals indicative of the digits in the sum or difference of the two partial numbers supplied to said circuit and an input carry or borrow of one, said last-mentioned circuits each providing at a fourth output connection signals indicative of the carry or borrow resulting from the addition or subtraction, respectively, of the two p-artial numbers supplied thereto andV an input carry or borrow of one, an output circuit, gate means connecting said lirst and third output connections of said circuits to said output circuit, said gate means Vbeing responsive to carry or borrow signals at'said secondV and fourth output connections to permit the passage lof the sum or difference signals from'onlyV a selectedv one of 'the two sum output connections of each circuit to said `a like plurality of partial numbers, each of said adder circuits receiving signals representing a partial number taken from said first mnnber and a corresponding partial number taken from said second number, each of said adder `circuits providing at a first output connection signals indicative of the digits in the sum of the two partial numbers applied tosaid adder circuit, each of said adder circuits providing at a second output connection signals indicative of the carryiresulting from the addition of the two partial numbers supplied thereto, each of said adder circuits except the adder circuit receiving vthe lowest order partial numbers providing at a third output connection signals indicative of the digits in the sum of the two partial numbers supplied to said adder circuit and an input carry of one, said last-mentioned adder circuits each providing at a fourth output connection signals indicative of the carry resulting from the addition of the two partial numbers supplied thereto and an input carry of one, an output circuit, gate meansV connecting said first and third output connections of said adder circuits to said output circuit, said gate means being responsive to carry signals at said second and fourth output connections to permit the passage of the sum signals from only a selected one of the two sum output connections of each Aadder circuit to said output circuit.

6. A parallel binary adder comprising a plurality of groups of adder stages, means for distributing the signals indicative of the individual digits of first and second numbers to be added among said groups, each of said groups receiving signals representing a first partial number comprising a selected succession of digits of said first number and a second partial number comprising the corresponding succession of digits of said second number, at least one of said partial numbers comprising more than one digit, the stages in the group receiving signals representing the lowest order digits being arranged in a single multi-digit adder circuit, said single circuit providing at separate outputs signals indicative of the sum and carry, respectively, resulting Vfrom the addition ofthe two partial numbers supplied thereto, each of said groups except said last-mentioned group being arranged in two multi-digit adder circuits, each circuit of each group receiving signals representing said first and second partial numbers supplied to said group, one circuit providing at separate outputs signals indicative, respectively, of thersum and carry resulting from the addition of the two partial numbers supplied thereto, .the other circuit providing signals indieiative ofthe sum and carry resulting from the addition of the two partial numbers supplied thereto and an input carry of one, an output circuit, and gate means connecting the sum outputs of each of said adder circuits to said output circuits, saidV gate means being responsive to the carry output signals of the several adder circuits to permit the passage of the sum signals fromonly aselected one ofthe adder circuits of each group torsaid output circuit. i

7. An improved lsubtracter system comprising fr subtracter circuits, at least onek of said subtracter circuits being a multidigit subtracter circuit, where n is an integer greater than one, means for distributing signals indicative of the individual digits of first and seco-nd numbers to be subtracted among Ysaid subtracter circuits, each of said numbers being divisible into n groups of digits, each digit group including at least one digit, at least one digit group including more than Vone digit, each of said subtracter circuits receiving signals representing ardigit group asta-1G81 of-said Vlirst number and a corresponding digit grouprof said second number, the subtracter circuit receivingrthe lowest order digit groups of said first and second numbers providing at `a first output connection signals indicative of the digits in the difference of the two digit groups supplied thereto and further providing at a second output connection signals indicative of the borrow resulting from the subtraction of the two digit groups supplied thereto, each ofthe other subtracter circuits providing similar signals at iirst and second output connections thereof and further providing at a third output connection signals indicative of the digits in the difference of the two digit groups supplied thereto yand an input borrow of one and also providing at` a fourth output connection signals indicative of the borrow resulting from the subtraction of the two digit groups supplied thereto and an input borrow of one, `an output circuit, n iirst gate means each connecting said iirst output connection of a corresponding one of said subtracter circuits to said output circuit, n--l second gate means each connecting circuit third output connections of a corresponding one of said subtracter circuits to said output circuit and means associated with said second and said fourth output connections of said subtracter circuits for controlling the operation of said rst and second gate means.

8. An improved adder system comprising n adder circuits, where n is an integer greater than one, means for distributing signals indicative of the individual digits of lirst and second numbers to be added among said adder stages, each of said numbers being divisible into n groups of digits, each digit group including at least one digit, at least one of said digit groups including more than one digit,'each of said adder circuits receiving signals Vrepresenting a `digit group of said iirst number and a corresponding digit group of said second number,the adder circuit receiving the lowest order digit groups of said first and second numbers providing at a rst output connection signals indicative of the digits in the sum of the two digit groups supplied thereto and furtherproviding at a second output connection signals indicative of the carry resulting from the addition of the two digit circuits supplied thereto, each of theotheradder groups providing similar signals at Viirst and second output connections thereof and further providing at a third output connection signals indicative of the digits in the'sum of the two digit groups supplied thereto and an input carry ofrone and also providing at a fourth output connection signals indicative of the carry resulting from the addition -of the two digit groups supplied thereto and an input carry of one, an output circuit, n Vfirst gate means each connecting said iirst output connection of a corresponding one of said adder circuits to said output circuit, n-l second gate means each connecting said third output connections of a corresponding one'of said'adder circuits to said output circuit and means associated with said ,second and said fourth output connections of said adder circuits for controlling the operation of said lirst and second gate means. Y- f 9. An improved combined adder-subtracter circuit comprising n adder-subtracter groups where n is VVan integer greater than one, means for distributing signals indicative of the individual digits of iirst and second numbers to be added or subtracted among said adder-subtracter groups, each of said numbers being divisible into n groups of digits, each digit group including atleast one` digit,

each of said adder-subtracter groups receiving signals rep- `resenting a digit group of said rst number and a corresponding digit group of said second number, means for setting said adder-subtracter groups, selectively, to add or subtract, the adder-subtracter group receiving the lowest order digit groups being arranged to provide a set of output signals, said set including signals representing the digits in the sum or diierence and carry or borrow resulting from the addition or subtraction, respectively, of the two digit groups Ysupplied thereto, each of said other 22 adder-subtracter groups being arranged to provide rst and second sets of output signals, said rst set including signals representing the digits in the sum or difference and carry or borrow resulting from the addition or subtraction, respectively, of the two digit groups supplied thereto, and said second set including signals representing the digits in the sum or difference and carry or borrow resulting fromv the addition or subtraction, respectively, of the two digit groups supplied thereto and an input carry or borrow of one, meansresponsive to the carry or borrow output of said adder-subtracter group receiving the lowest order digit groups for selecting one of said two sets of signals in the next higher order addersubtracter group, means responsive to the-carry or bor'- row signal in the selected set of each of said other groups for selecting one of said two sets of signals of the next higher group, an output circuit and means for supplying the sum or'difference signals of said lowest ordergroup and the sum or difference signals in the selected s ets of all said other groups to said output circuit. Y

10. An improved adder circuit comprising n adder groups where n is an integer greater than one, means-for distributing signals indicative of the indvidual digits of first and second numbers to be added among said4 adder groups, each of said numbers being divisible into n groups of digits, each digit group including at least one digit, eachy of said adder groups receiving signals representing a digit group of said 'rst number and a corresponding digit group of said second number, the adder group receiving the lowest order digit groups being arranged to provide a set of output signals, said set including signals representing the digits in the sum and carry resulting rom the addition of the two digit groups supplied thereto, each of said other adder groups being-arranged to provide rst and second sets of output signals, said iirst set including signals representing the digits Ain the sum and carry resulting from the addition of the two digit groups supplied thereto, and said second set including signals representing the digits in the sum and carry Aresulting from the addition of the two digit groups supplied thereto andan input carry of one, means responsive to the carry output of said adder group receiving the lowest order digit groups for selecting onetof said two sets of signals in the next higher order adder group, means responsive to the carry signal-in the selected vset ofY each of said other groups for selecting one of said two sets of signals of the next higher group, an output circuit and means for supplying the sum signals of said lowest order group and the sum signals in the selected sets of all said other groups to said output circuit. ,I 11-. An improved subtracter circuit comprisingn subtracter groups where n is an integer greater than one, means for distributing signals indicative of the individual digits of iirst and second numbers to be subtracted among Y said subtracter groups, each of said numbers Vbeing divisible into n groups of digits, each digit group including at least one digit, each of said subtracter groups receiving signals representing a digit group of said iirst number and a corresponding digit group of said second number, the subtracter group receiving the lowest order digit groups being arranged to provide a set of output signals, said set including signals representing the digits in the difference and borrow resulting from the subtraction of the two digit groups supplied thereto, each of said other subtracter groups being arranged to provide irst and second sets `of output signals, said first set including signals representing the digits in the difference and borrow resulting from the subtraction of the two digit groups supplied thereto, and said second set including signals representing the digits in the dierence and borrowlresulting from the subtraction of the two digit groups supplied thereto and an input borrow of one, means responsive tothe borrow output of said subtracter group receiving the lowest order digit groups for selecting one of said two sets of signals in the next higher order sub-I t-racter group, means responsive to the borrow signal in the selected set of each of said other groups for selecting one of said two sets of signals of the next higher group, an output circuit and means for supplying the difference signals of said lowest order group Vand the difference signals in the selected sets of all said other groups to said output circuit.

' 12. An improved adder circuit comprising n adder groups where n is an integer greater than one, means for distributing signals indicative of the individual digits of iirst Vand secondV numbers to 'be added among said adder groups, each ofY said numbers being divisible into n groups of digits, each digit group including at least one digit, each of said adder groups receiving signals representing a digit group of said first number and a corresponding digit group of said ,second number, the adder group receiving the lowest order digit group having a rst set of outputs including first and second outputs, said iirst output supplying signals indicative of the carry and said second output supplying signals indicative of the digits in the sum resulting from the addition of the two digit groups supplied thereto, the others of said adder groups having a first set of outputs corresponding to said aforementioned first set of outputs and a second set of outputs including third and fourth outputs, said third output supplying signals indicative of the carry and said forth output supplying signals indicative or the digits of the sum resulting from the addition of the two digit groups supplied thereto and an input carry of one, means connecting said rst output and said third output, if present, of each adder group to the next higher order adder group, an output circuit, means connecting said second output and said fourth output, if present, of each adder group to said output circuit, each of said other adder groups including means associated therewith and responsive to a signal indicative of a carry of zero from the next lower order adder group for blocking signals from said second set of outputs of the adder group associated therewith and responsive to a signal indicative of a carry of one from the next lower order adder group for blocking signals from said rst set of outputs of the adder group associated therewith.

13. An improved adder-subtracter circuit comprising n adder-subtracter groups where n is an integer greater thanV one, means for setting said groups, selectively, to add or subtract, means for distributing signals indicative of the individual digits of first and second numbers to be combined among said adder-subtracter groups, each of said numbers being divisible to n groups of digits, each digit group including at least one digit, each of said adder-subtracter groups receiving signals representing a digit` group of said first number and a corresponding digit group of said second number, the adder-subtracter group receivingthe lowest order digit group having a first set of outputs including tirst and second outputs, said first output supplying signals indicative of the carry-borrow and said Vsecond output supplying signals indicative of the digits in the Sum-difference resulting from the addition-subtraction of the two digit groups supplied thereto, the others of said adder-subtracter groups having a first set of outputs corresponding to said aforementioned iirst set of outputs and a second set of outputs including third and fourth outputs, said third output supplying signals indicative of the carry-borrow and said fourth output supplying signals indicative of the digits of the sum-difference resulting from the addition-subtractionrof the two digit groups supplied thereto and at input carry-borrow of one, means connecting said first output and said third output, if present, of each adder-subtracter group to the next higher order adder-subtracter group, an output circuit, means connecting said second output and said fourth output, if present, of each adder-subtracter group to said output circuit, each of said other adder-subtracter groups including means associated therewith and responsive to a signal indicative of a 'carry-borrow of zero vfrom Y 24 i t the next lower order adder-subtracter group forblocking signals from said `second set of outputs of the addersubtracter group associated therewith and responsive to lower order adder-subtracter group for blocking signals from said first set of outputs of the adder-subtracter group associated therewith. l

14. An arithmetic computation circuit having a shortened carry propagation time, comprising means for dividing each of two numbers to be combined into n corresponding digit groups,V at least one of said digit groups including more than one digit, a first plurality of means for combining each digit group of one number with the corresponding digit group of the other number by an arithmetic operation selected from the group comprising addition and subtraction and with an input carry-borrow digit of Zero, a second plurality of means for simultaneously combining each digit group except the lowest order digit group of said first number with'the corresponding digit group of the other number by the same arithmetic operation and with an assumed inputcarryborrow digit of.o11e to each group, thereby to provide a rst result signal and a corresponding output carryborrow digit signal for the lowest orderl group and a tirst result signal and a corresponding output carryborrow digit signal and a second result signal and a corresponding output carry-borrow digit signal for each group except Said lowest order group, means for supplying the result signal of said combining means for said lowest order group to said output circuit, means responsive to the output carry-borrow digit signal of the vcornbin'ing means for said lowest order group for supplying only a selected one of said result signals of the combining means of the next higher order group to said output circuit, the result signal selected being determined by the value of the output carry-borrow digit signal supplied by said combining means for said lowest order group, means responsive to the output carry-borrow digit signal corresponding to the selected result signal of each of said combining means except said lowest order combining means for supplying only a selected result signal of the next higher order combining means to said output circuit, the result signal selected being determined by the value of the output carry-borrow digit signal corresponding to the selected result signal of the combining means for the Vlower order group.

15. A parallel adder circuit having a shortening carry propagation time, comprising means for dividing each of two numbers to be added into n corresponding digit groups, at least one of said digit groups for each number including more than one digit, a first plurality of means for adding each digit group of one number to the corresponding digit group of the other number with an assumed carry input of Zero, a second plurality of means for simultaneously adding each digit group except the lowest order digit group of said first number to the corresponding digit group of the other number with au assumed carry input of one to each group, thereby to provide arst sum signal and a carry signal for said lowest order group and to provide a rst sum signal and a corresponding carry signal anda second sum signal and a corresponding carry signal for each group except said lowest order groupan 4output circuit, means for supplying the sum signal of said adding means for said lowest order digit group to said output circuit, means responsive to the carry output signal of the adding means for said lowest order digit group for supplying only one sum signal of the adding means for the next higher order digit group to said output circuit, the sum signal selected being determined by the value of the carry output signal of the adding means for said lowest order digit group, and means lresponsive to the carry output signals corresponding to the selected sum signals of each of said adding means except said lowest order adding means 'for supplying a selected sum signal of the next higher order `adding means to said output circuit, the sum signal selected being determined by the value of the output carry signal of the adding means for the lower order adding means.

16. An arithmetic computation system comprising a plurality of computation circuits each arranged to perform the same arithmetic function, said arithmetic function being a single arithmetic function chosen from the two arithmetic functions addition and subtraction, means for distributing signals indicative of the individual digits of rst and second mu-ltidgit numbers to be combined among said computation circuits, each of said two numbers being divisible into a like plurality .of partial numbers, said signal distributing means supplying to each of said computation circuits signals representing a partial number derived from said iirst number and a corresponding partial number derived from said second number, the partial numbers supplied to at least one of said computation circuits comprising a multidigit partial number, each of said computation circuits providing at a first output connection signals indicative of the digits generated in the result of the performance of said selected function on the two partial numbers supplied to that computation circuit, each of said computation circuits providing at a second output connection signals indicative of the carry-borrow digit generated in the performance of said selected function, each of said computation circuits except the computation circuit receiving the lowest order partial numbers providing at a third output connection signals indicative of the result digits generated in the performance of said selected function upon the two partial numbers supplied to that computation circuit and yan input carry-borrow digit of one, said last-mentioned computation circuits each providing at a fourth output connection signals indicative of the carry-borrow digit generated from the performance of said selected function on the two partial numbers supplied thereto and an input carry-borrow digit of one, an output circuit, signal actuatable gate means connecting said first and third output connections of said computation circuits to said output circuit, and means connecting said second and fourth output connections of said computation circuits to control inputs of selected ones of said gate means, said gate means being responsive to said carryborrow digit signals at said second and fourth output connections to permit the result digit signals from only a selected one of said rst and third output connections of each of said computation circuits to pass to said output circuits.

References Cited in the le of this patent UNITED STATES PATENTS 2,364,540 Luhn Dec. 5, 1944 2,601,281 Hartley et al. June 24, 1952 2,609,143 Stibitz Sept. 2, 1952 2,734,684 Ross et al Feb. 14, 1956 2,803,401 Nelson --a.i-. Aug. 20, 1957 

